# QUAD02 Series and QUAD04 Series

The QUAD02 Series includes the following hardware:

- PCM-QUAD02
- CIO-QUAD02

The QUAD04 Series includes the following hardware:

- PCI-QUAD04
- CIO-QUAD04

The QUAD02 Series and QUAD04 Series support the following UL and UL for .NET features.

## Counter I/O

Functions

UL: cbC7266Config(), cbCIn(), cbCIn32(), cbCLoad(), cbCLoad32(), cbCStatus()

UL for .NET: C7266Config(), CIn(), CIn32(), CLoad(), CLoad32(), CStatus()

CounterNum

PCM-QUAD02, CIO-QUAD02: 1 to 2

CIO-QUAD04, PCI-QUAD04: 1 to 4

RegNum

UL: COUNT1, COUNT2, PRESET1, PRESET2, PRESCALER1, PRESCALER2

UL for .NET: QuadCount1, QuadCount2, QuadPreset1, QuadPreset2, QuadPreScaler1, QuadPreScaler2

CIO-QUAD04, PCI-QUAD04 also support:

UL: COUNT3, COUNT4, PRESET3, PRESET4, PRESCALER3, PRESCALER4

UL for .NET: QuadCount3, QuadCount4, QuadPreset3, QuadPreset4, QuadPreScaler3, QuadPreScaler4

Note: COUNTx is used to initialize the LS7266 counter type. Load this value FIRST if using the PRESETx or PRESCALERx registers.
PRESCALERx is used for clock filtering for the LS7266 counter type. Valid values are 0 to 255. If using the PRESETx or COUNTx registers, load this value LAST.

LoadValue

When using cbCLoad32() to load the COUNT or PRESET registers, values up to 16.78 million (224 – 1) may be loaded. With the PCM-QUAD02 and PCI-QUAD04, load Prescaler last for proper operation.
Values using cbCLoad() and CLoad() are limited to 65,535 (216 – 1). Refer to the Basic signed integers discussion in the Counter Hardware topic. When loading the PRESCALER register, values may be from 0 to 255.

Digital Filter Clock frequency = 10 megahertz (MHz) / LoadValue + 1.

## Hardware Considerations

##### Loading and reading 24-bit values

The QUAD series boards feature a 24-bit counter. You can use the cbCIn()/CIn() and cbCLoad()/CLoad() functions for counts that are less than 16 bits (65,535), or use the cbCIn32()/CIn32() and cbCLoad32()/CLoad32() functions for any number supported by the LS7266 counter (24 bits = 16777216).

When using cbCLoad32() to load COUNT and PRESET registers on the PCM-QUAD02 and PCI-QUAD04, load Prescaler last for proper operation.

##### Cascading counters (PCI-QUAD04 only)

The PCI-QUAD04 can be set up for cascading counters. By setting the appropriate registers, the following configurations are possible:

- Four 24-bit counters, or
- Two 48-bit counters, or
- One 24-bit and one 72-bit counters, or
- One 96-bit counter

The OUTPUT pins of a counter are directed to the next counter by setting FLG1 to CARRY/BORROW, and FLG2 to UP/DOWN. Bits 3 and 4 of the IOR Register control are set to 1,0 to accomplish this.

You can set these bits by using the functions cbC7266Config(BoardNum, CounterNum, Quadrature, CountingMode, DataEncoding, IndexMode, InvertIndex, FlagPins, and GateEnable). When using the Universal Library for .NET, use the C7266Config() method.

The constant CARRYBORROW_UPDOWN (value of 3) is used for the FlagPins parameter.

The IOR register cannot be read. However, you can read the values of the BADR2+9 register. The value for Base 2 can be determined by looking at the resources used by the board. The 8-bit region is BADR2. The BADR+9 register contains values for PhxA and PhxB, for x = 1 to 4 to identify counters. The diagram below indicates the routing of the FLG pins depending on the value of PhxA and PhxB. The actual values of the BADR2+9 register are shown below:

Register BADR2 + 9 D0-D6
| PH2A | PH2B | PH3A | PH3B | PH4A | PH4B1/PH4B0 | Value
Case1: (4) 24-bit counters (1/2/3/4) | 0 | 0 | 0 | 0 | 0 | 0,0 | 0.0
Case2: (2) 48-bit counters (1-2/3-4) | 1 | 1 | 0 | 0 | 1 | 1,0 | 53
Case3: (1) 24-bit counter and (1) 72-bit counter (1/2-3-4) | 0 | 0 | 1 | 1 | 1 | 0,1 | 3C
Case4: (1) 96-bit counter (1-2-3-4) | 1 | 1 | 1 | 1 | 1 | 0,1 | 3F
Defaults to 0x00 (no inter-counter connections).

Examples
Case 1: | (4) 24-bit counters (1/2/3/4) cbC7266Config(0,1,0,0,2,0,0,1,0) cbC7266Config(0,2,0,0,2,0,0,1,0) cbC7266Config(0,3,0,0,2,0,0,1,0) cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 2: | (2) 48-bit counters (1-2/3-4) cbC7266Config(0,1,0,0,2,0,0,3,0) cbC7266Config(0,2,0,0,2,0,0,1,0) cbC7266Config(0,3,0,0,2,0,0,3,0) cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 3: | (1) 24-bit counter and (1) 72-bit counter (1/2-3-4) cbC7266Config(0,1,0,0,2,0,0,1,0) cbC7266Config(0,2,0,0,2,0,0,3,0) cbC7266Config(0,3,0,0,2,0,0,3,0) cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 4: | (1) 96-bit counter (1-2-3-4) cbC7266Config(0,1,0,0,2,0,0,3,0) cbC7266Config(0,2,0,0,2,0,0,3,0) cbC7266Config(0,3,0,0,2,0,0,3,0) cbC7266Config(0,4,0,0,2,0,0,1,0)
The actual value of the BADR+9 register is not set until the cbCLoad()/CLoad() command is called.

##### Counter4 setting

Setting Counter4 to CARRYBORROW-UPDOWN is NOT VALID.