# PCI-DAS4020/12

## Analog Input

Functions

UL: cbAIn(), cbAInScan(), cbATrig(), cbAPretrig(), cbFileAInScan(), cbFilePretrig()

UL for .NET: AIn(), AInScan(), ATrig(), APretrig(), FileAInScan(), FilePretrig()

Options

BACKGROUND, CONTINUOUS, EXTCLOCK, CONVERTDATA, SINGLEIO, DMAIO, BLOCKIO*, EXTTRIGGER

*The packet size is based on the Options setting:

Options setting | Packet size
BLOCKIO | 2,048

HighChan

3 max. When scanning multiple channels, the number of channels scanned must be even.

Rate

Up to 20000000. The minimum value for Rate is 1000. Note that contiguous memory is no longer required to achieve the maximum sample rate.

Range

BIP5VOLTS (±5 volts)

BIP1VOLTS (±1 volts)

## Analog Output

Functions

UL: cbAOut(), cbVOut(), cbAOutScan()

UL for .NET: AOut(), VOut(), AOutScan()

Options

NONE

HighChan

1 max

Count

2

Rate

Ignored

Range

BIP10VOLTS (±10 volts)

BIP5VOLTS (±5 volts)

DataValue

0 to 4,095

Pacing

Software only

## Digital I/O

Functions

UL: cbDOut(), cbDIn(), cbDBitIn(), cbDBitOut(), cbDConfigPort()

UL for .NET: DOut(), DIn(), DBitIn(), DBitOut(), DConfigPort()

PortNum

FIRSTPORTA, FIRSTPORTB, FIRSTPORTCL, FIRSTPORTCH

DataValue

0 to 255 for FIRSTPORTA or FIRSTPORTB

0 to 15 for FIRSTPORTCL or FIRSTPORTCH

BitNum

0 to 23 for FIRSTPORTA

## Counter I/O

Functions

No counter functions are supported.

## Triggering

Functions

UL: cbSetTrigger()
UL for .NET: SetTrigger()

TrigType

TRIGPOSEDGE, TRIGNEGEDGE, TRIGABOVE, TRIGBELOW, GATEHIGH, GATELOW, GATENEGHYS, GATEPOSHYS, GATEABOVE, GATEBELOW, GATEINWINDOW, GATEOUTWINDOW

Threshold

0 to 4,095

## Event Notification

Functions

UL: cbDisableEvent(), cbEnableEvent()

UL for .NET: DisableEvent(), EnableEvent()

Types

ON_SCAN_ERROR, ON_PRETRIGGER*, ON_DATA_AVAILABLE, ON_END_OF_INPUT_SCAN

*Note that the EventData for ON_PRETRIGGER events may not be accurate. In general, this value will be below the actual number of pretrigger samples available in the buffer.

## Hardware Considerations

##### EXTCLOCK

An approximation of the rate is used to determine the size of the packets to transfer from the board. When the EXTCLOCK option is used, set the Rate argument to an approximate maximum value.

##### Pacing analog input

Hardware pacing, external or internal clock supported. The clock source can be set via InstaCal to either the "Trig/Ext Clk" BNC input or the "A/D External Clock" input on the 40 pin connector (P3). Configuring for the BNC clock input will disable the clock input (pin 10) on the 40-pin connector. When the EXTCLOCK option is used, the clock signal presented to the "Trig/Ext Clk" BNC input or the "A/D External Clock" input is divided by 2 in one or two channel mode, and is divided by 4 in four channel mode. If both EXTCLOCK and EXTTRIGGER are used, both the Trigger BNC and pin 10 on the 40-pin connector require signals. This is further explained in the Triggering section below.

When using EXTCLOCK, the Rate argument is used by the Universal Library to calculate the appropriate chain size; set the Rate argument to the approximate rate that the external clock will be pacing acquisitions.

When executing cbAInScan()/AInScan() with the EXTCLOCK option, the first three clock pulses are used to set up the PCI-DAS4020/12, and the first sample is actually taken on the fourth clock pulse.

##### Triggering and gating

Digital (TTL) hardware triggering supported. The trigger source can be set via InstaCal to either the "Trig/Ext Clk" BNC input, the "A/D Start Trigger" input on the 40-pin connector (P3) or the "A/D Stop Trigger" input on the 40-pin connector (P3). Use the A/D Start Trigger input for the cbAInScan() and cbFileAInScan() functions, and AInScan() and FileAInScan() methods. For the cbAPretrig() or cbFilePretrig() functions, and the APretrig() or FilePretrig() methods, use the A/D Stop Trigger input.

When using both EXTCLOCK and EXTTRIGGER options, one of the signals (either clock or trigger) must be assigned to the Trig/Ext Clk BNC input. The function of the Trigger BNC is determined by the setting of "Trig/Ext Clock Mode" in InstaCal. The Trig/Ext Clock BNC can be set to function as either the trigger ("A/D Start Trigger") or the clock ("A/D External Clock"). Pin 10 on the 40-pin connector then assumes the opposite function.

Analog hardware triggering supported. The trigger source can be set via InstaCal to any of the analog BNC inputs. cbSetTrigger()/SetTrigger() is supported for TRIGBELOW and TRIGABOVE trigger types. Analog thresholds are set relative to the voltage range set in the scan. For example, using a range of BIP1VOLTS during a cbAInScan()/AInScan(), (0) corresponds to -1V and 4,095 corresponds to +1V.

When using the cbAPretrig() function or the APretrig() method, use either the TRIGGER BNC or pin 8 of the 40 pin connector. To use the BNC, set the InstaCal option "Trig/Ext Clock Mode" to A/D Stop Trigger; otherwise, if not set to this selection, pin 8 of the 40-pin connector is used.

When using cbAPretrig()/APretrig() with EXTCLOCK, the two inputs are required. The TRIGGER BNC can be set to function as either the pacer clock or the trigger. For the BNC to be setup as the pacer clock, set the InstaCal option "Trig/Ext Clk Mode" to A/D External Clock. To use the BNC as the trigger, set this InstaCal option to A/D Stop Trigger. If neither of these selections are used, the 40-pin connector will be used for both inputs; pin 8 will be input for A/D Stop Trigger, and pin 10 will be input for the pacer clock signal.

Digital (TTL) hardware gating supported. The gate source can be set via InstaCal to either the "Trig/Ext Clk" BNC input or the "A/D Pacer Gate" input on the 40-pin connector (P3).

Analog hardware gating supported. Analog thresholds are set relative to the voltage range set in the scan. For example, using a range of BIP1VOLTS during a cbAInScan()/AInScan(), (0) corresponds to (–1V) and 4,095 corresponds to +1V.

The gate must be in the active (enabled) state before starting an acquisition.

For EXTCLOCK or EXTTRIGGER (digital triggering) using the BNC connector, InstaCal provides a configuration setting for thresholds. The selections available are either 0 volts (V) or 2.5 volts (V). Use 0 volts if the incoming signal is BIPOLAR. Use the 2.5 volts option if the signal is UNIPOLAR, such as standard TTL.

When using both EXTCLOCK and EXTTRIGGER options, one of the signals (either clock or trigger) must be assigned to the Trig/Ext Clk BNC input.

##### Sample Size Requirements

With the following functions and methods, be aware of packet size, and adjust the number of samples acquired accordingly:

- cbAPretrig(), APretrig()
- cbAInScan(), AInScan() with the CONTINUOUS scan option

These functions and methods use a circular buffer. Align the data by packets in the buffer. The total number of samples must be greater than one packet , and must be an integer multiple of packet size; refer to the following table. The minimum value for contiguous memory is calculated as:

( # of KB ) = {( # of samples ) ÷ 512}

For example, to run cbAInScan() on one channel at 18 MHz with the CONTINUOUS option set, the minimum sample size from the table below is 262,144, since the Rate is between 14 and 20 MHz. The minimum contiguous memory is then calculated as:

(262,144 ÷ 512 ) = 512 KB

# of channels | Rate in MHz | Packet size in samples | Minimum sample size (2 packets)
1 | 20 ≥ Rate ≥ 13.3 | 131,072 | 262,144
13.3 > Rate > 4 | 65,536 | 131,072
4 ≥ Rate ≥ 2 | 4,096 | 8,192
2 > Rate | 2,048 | 4,096
2 | 20 ≥ Rate ≥ 6.6 | 131,072 | 262,144
6.6 > Rate ≥ 2 | 65,536 | 131,072
2 > Rate ≥ 1 | 4,096 | 8,192
1 > Rate | 2,048 | 4,096
4 | 10 ≥ Rate ≥ 3.3 | 131,072 | 262,144
3.3 > Rate ≥ 1 | 65,536 | 131,072
1 > Rate ≥ 0.5 | 4,096 | 8,192
0.5 > Rate | 2,048 | 4,096