# cbSelectSignal()

Configures timing and control signals to use specific Auxiliary or DAQ Sync connections as a source or destination.

This function is intended for advanced users. Except for the SYNC_CLK input, you can easily configure all the timing and control signals using InstaCal.

Note: This function is not supported by all board types. Please refer to board specific information for details.

## Function Prototype

C/C++

int cbSelectSignal(int BoardNum, int Direction, int Signal, int Connection, int Polarity);

Visual Basic

Function cbSelectSignal(ByVal BoardNum&, ByVal Direction&, ByVal Signal&, ByVal Connection&, ByVal Polarity&) as Long

## Arguments

BoardNum

The number associated with the board when it was installed with InstaCal or created with cbCreateDaqDevice(). BoardNum may be 0 to 99. The board must have configurable signal inputs and outputs.

Direction

Direction of the specified signal type to be assigned a connector pin. For most signal types, this should be either SIGNAL_IN or SIGNAL_OUT. For the SYNC_CLK , ADC_TB_SRC and DAC_TB_SRC signals, the external source can also be disabled by specifying DISABLED(=0) such that it is neither input nor output. Set it in conjunction with the Signal, Connection, and Polarity arguments using the information listed in the Direction argument values section below.

Signal

Signal type to be associated with a connector pin. Set it to one of the constants listed in the "Signal argument values" section below.

Connection

Designates the connector pin to associate the signal type and direction. Since individual pin selection is not allowed for the DAQ-Sync connectors, all DAQ-Sync pin connections are referred to as DS_CONNECTOR. The AUXIN and AUXOUT settings match their corresponding hardware pin names.

Polarity

ADC_TB_SRC and DAC_TB_SRC input signals (SIGNAL_IN) can be set for either rising edge (POSITIVEEDGE) or falling edge (NEGATIVEEDGE) signals. The AUXOUT connections can be set to INVERTED or NONINVERTED from their internal polarity.

## Returns

- Error code or 0 if no errors.

### Signal argument values

Signal | Connection
ADC_CONVERT | A/D conversion pulse or clock.
ADC_GATE | External gate for A/D conversions.
ADC_SCANCLK | A/D channel scan signal.
ADC_SCAN_STOP | A/D scan completion signal.
ADC_SSH | A/D simultaneous sample and hold signal.
ADC_STARTSCAN | Start of the A/D channel-scan sequence signal.
ADC_START_TRIG | A/D scan start trigger.
ADC_STOP_TRIG | A/D stop- or pre- trigger.
ADC_TB_SRC | A/D pacer timebase source.
CTR1_CLK | CTR1 clock source.
CTR2_CLK | CTR2 clock source.
DAC_START_TRIG | D/A start trigger.
DAC_TB_SRC | D/A pacer timebase source.
DAC_UPDATE | D/A update signal.
DGND | Digital ground.
SYNC_CLK | STC timebase signal.

### Direction argument values

Valid input (Direction=SIGNAL_IN) connection pin and polarity settings include:

Signal | Connection | Polarity
ADC_CONVERT | AUXIN0..AUXIN5 DS_CONNECTOR | POSITIVEEDGE or NEGATIVEEDGE
ADC_GATE | AUXIN0..AUXIN5 | See cbSetTrigger()
ADC_START_TRIG | AUXIN0..AUXIN5 DS_CONNECTOR | See cbSetTrigger()
ADC_STOP_TRIG | AUXIN0..AUXIN5 DS_CONNECTOR | See cbSetTrigger()
ADC_TB_SRC | AUXIN0..AUXIN5 | POSITIVEEDGE or NEGATIVEEDGE
DAC_START_TRIG | AUXIN0..AUXIN5 DS_CONNECTOR | Not assigned here.
DAC_TB_SRC | AUXIN0..AUXIN5 | POSITIVEEDGE or NEGATIVEEDGE
DAC_UPDATE | AUXIN0..AUXIN5 DS_CONNECTOR | POSITIVEEDGE or NEGATIVEEDGE
SYNC_CLK | DS_CONNECTOR | Not assigned here.

Valid output (Direction=SIGNAL_OUT) connection pin and polarity settings include:

Signal | Connection | Polarity
ADC_CONVERT | AUXIN0..AUXIN2 DS_CONNECTOR | INVERTED* or NONINVERTED
ADC_SCANCLK | AUXIN0..AUXIN2
ADC_SCAN_STOP | AUXIN0..AUXIN2
ADC_SSH | AUXIN0..AUXIN2
ADC_STARTSCAN | AUXIN0..AUXIN2
ADC_START_TRIG | AUXIN0..AUXIN2 DS_CONNECTOR
ADC_STOP_TRIG | AUXIN0..AUXIN2 DS_CONNECTOR
CTR1_CLK | AUXIN0..AUXIN2
CTR2_CLK | AUXIN0..AUXIN2
DAC_START_TRIG | AUXIN0..AUXIN2 DS_CONNECTOR
DAC_UPDATE | AUXIN0..AUXIN2 DS_CONNECTOR
DGND | AUXIN0..AUXIN2 | Not assigned here.
SYNC_CLK | DS_CONNECTOR

* INVERTED is only valid for Auxiliary Output (AUXOUT) connections.

Valid disabled settings (Direction=DISABLED):

Signal | Connection | Polarity
ADC_TB_SRC | Not assigned here. | Not assigned here.
DAC_TB_SRC
SYNC_CLK

### Notes

- You can view and edit the above timing and control configuration information from InstaCal. Open InstaCal, click on the board, and press the "Configure..." button or menu item. If the board supports DAQ Sync and Auxiliary Input/Output signal connections, a button labeled "Advanced Timing & Control Configuration" displays. Press that button to open a display for viewing and modifying the above timing and control signals.
- Except for the ADC_TB_SRC, DAC_TB_SRC and SYNC_CLK signals, selecting an input signal connection does not necessarily activate it. However, assigning an output signal to a connection does activate the signal upon performing the respective operation. For instance, when running an EXTCLOCK cbAInScan(), ADC_CONVERT SIGNAL_IN selects the connection to use as an external clock to pace the A/D conversions; if cbAInScan() is run without setting the EXTCLOCK option, however, the selected connection is not activated and the signal at that connection is ignored. In both cases, the ADC_CONVERT signal is output via the connection(s) selected for the ADC_CONVERT SIGNAL_OUT. Since there are no scan options for enabling the Timebase Source and the SYNC_CLK, selecting an input for the A/D or D/A Timebase Source, or SYNC_CLK does activate the input source for the next respective operations.
- Multiple input signals can be mapped to the same AUXINn connection by successive calls to cbSelectSignal; however, only one connection can be mapped to each input signal. If another connection had already been assigned to an input signal, the former selection is de-assigned and the new connection is assigned.
- Only one output signal can be mapped to the same AUXOUTn connection; however, multiple connections can be mapped to the same output signal by successive calls to cbSelectSignal. If an output signal had already been assigned to a connection, then the former output signal is de-assigned and the new output signal is assigned to the connection. Note that there are at most MAX_CONNECTIONS(=4) connections that can be assigned to each output signal.
- When selecting DS_CONNECTOR for a signal, only one direction per signal type can be defined at a given time. Attempting to assign both directions of a signal to the DS_CONNECTOR results in only the latest selection being applied. If the signal type had formerly been assigned an input direction from the DS_CONNECTOR, assigning the output direction for that signal type results in the input signal being reassigned to its default connection:

Default input signal connections
Input signal | Default connection
ADC_CONVERT | AUXIN0
ADC_GATE | AUXIN5
ADC_START_TRIG | AUXIN1
ADC_STOP_TRIG | AUXIN2
DAC_UPDATE | AUXIN3
DAC_START_TRIG | AUXIN3

- ADC_TB_SRC and DAC_TB_SRC are intended to synchronize the timebase of the analog input and output pacers across two or more boards. Internal calculations of sampling and update rates assume that the external timebase has the same frequency as its internal clock. Adjust sample rates to compensate for differences in clock frequencies.
- For instance, if the external timebase has a frequency of 10 MHz on a board that has a internal clock frequency of 40 MHz, the scan function samples or updates at a rate of about 1/4 the rate entered. However, while compensating for differences in external timebase and internal clock frequency, if the rate entered results in an invalid pacer count, the function returns a BADRATE error.