Getting started with the ADP2230

1. Hardware

To set up the ADP2230:

  1. First, install the Digilent WaveForms software on your PC. See Installer Details for more information.
  2. Connect the ADP2230 to your PC using a USB cable and optional connect 5 V DC auxiliary supply.

  Recommended operating conditions Absolute ratings
Oscilloscope (1,2) 50 V peak2peak, 1MΩ|24pF ±50 V
Wavegen (AWG 1) ±5 V, ≤30 mA, 50Ω ±10 V, 40 mA
Power Supplies (V+,V-) 0.5 ... 5 V, -0.5 ... -5 V, 0.8A/channel +6 V, -6 V, 1.6A/channel
   Voltage Readback -15V ... +15V -15V ... +15V
   USB powered 0.6W-5.5W total depends on PD
   Auxiliary powered 10W total 15W total
Digital IOs, Triggers (T1,T2,0,1...15) LVCMOS 3.3 V, 4-16 mA, slow-fast ± 20 V
USB Supply 5V, 0.9 ... 3A 4.5V ... 5.5V
Auxiliary Supply (5VDC) 5V, 4A, 20W 4.5V ... 5.5V, 3.1A, 15.5W

For more information visit the ADP2230 reference page.

 


2. Software

See Installer Details for information on installing WaveForms.

See WaveForms for information on using the software.

 

2.1 System Frequency

The system clock is adjustable between 50 and 125MHz. This will be the base frequency used for Oscilloscope, Wavegen, Logic Analyzer and Pattern Generator. Each instrument or channel rate will be derived from this frequency.

The internal clock can be scaled down and output on Trigger 1 and 2. The Trigger 1 input can be used as reference clock for the device.

To use external reference clock:

To use two ADP2230 devices together:

To use multiple devices together with separate WaveForms applications, custom application or script:

A dedicated low-jitter PLL (CDCE6214) is used to drive the ADC and DAC.
In standalone and master mode the CDCE6214 uses a local 25 MHz oscillator, providing to ADC a clock with less than 3ps jitter in 50Hz and 20MHz range.
A PLL in the FPGA is used to generate internal clocks, and also a low frequency clock which can be adjusted between 10 and 50MHz, and optionally output on the Trigger IOs.
The device can also be used in slave mode with external reference clock of 10-50MHz applied to Trig1, bypassing the FPGA and driving the CDCE6214. The minimum input reference frequency for the CDCE6214 is 10MHz. In this mode we measured less than 4ps jitter on ADC clock relative to the reference clock.

 


2.2 Configurations

The device has two real configurations, one with DDR-RAM and the other one disables this circuitry for lower power consumption, 3.7W vs 2.7W minimum consumption.

At least USB 3.1 Gen 1 port and cable is recommended, or USB 3.0 (SuperSpeed, 5 Gbps) and 5V DC auxiliary power supply is required to take advantage of higher speed communication. Without this, the lower power configuration with less device buffer will be used by default.

The following virtual configurations are available:


 


3. Troubleshooting

In case you receive the error message "Communication with device failed" or "Device configuration failed":

The ADP2230's system monitor displays the voltage, current, and temperature. In the main window, click the button in the status bar to show this information.

When no instrument is running, the device power consumption is around 3.8 W (750mA) with DDR RAM configuration and 2.8W (550mA) with BRAM. Depending on the usage, consumption can increase subject to the following limitations:

If you receive the previously mentioned error message, or if the voltage is less than 4.5 V, try the following options:

The LED on the font of the device is:

 


4. Oscilloscope

The ADP2230 has two BNC oscilloscope input channels.

Specifications:

 


5. Arbitrary Waveform Generator

The ADP2230 is equipped with one Arbitrary Waveform Generators channel.

Specifications:

 


6. Power Supplies

The ADP2230 has two adjustable power supplies.

Specifications:

The power supplies can be used as slow AWG channels, see Wavegen channel 2 and 3.

The power tree of the device contains 4 electronic fuses and several regulators.
The first 2 monitor the USB and AUX voltage and current. The USB supply is by default disabled when the AUX is supplied, see device options "USB Power".
The internal device power rails are split in digital and analog. The 3rd eFuse is internally used to enable the analog rails.
The 4th eFuse for the ±5V supplies is used as master enable switch, to monitor and set the total power limit for the user V+/- supplies.

 


7. Digital I/O

The ADP2230 has 16 Digital I/O (DIO 0-15) and 2 Trigger I/O channels.

Specifications: